LDMOS is one of the most commonly used devices in the RF process. Based on LDMOS, an RFLDMOS with low-cost, high-performance, and high-integration can be formed and applied in high-frequency communication field and other application fields requiring high speed. FIG. 1 shows the structure of a common RFLDMOS. How to reduce the parasitic capacitance in an insulating region to increase the response frequency of the device becomes a major technical difficulty. A common practice to reduce the parasitic capacitance in the insulating region is to greatly increase the thickness of a field oxide film. For the RFLDMOS typically used in 2.4 GHz or higher, the thickness of its oxide film is more than 1 μm. As the required thickness of the field oxidation is too large, the field oxidation can't be formed by STI process and is usually formed by LOCOS process, which will bring a large unevenness on the substrate after the field oxidation is completed and greatly limit the subsequent process, therefore, the production of small-size devices can't be realized. For example, for a 0.5 μm RFLDMOS used in 2.4 Ghz, the thickness of the field oxidation is usually more than 1 μm, typically 2-3 μm. Meanwhile the field oxidation is 0.5 μm higher than the substrate surface, and for a 0.5 μm gate, its lithography process window is 0.8˜1 μm. Therefore the substrate has a large unevenness, making the critical dimension of the device difficult to control and leading to a low yield product and a high production cost of the RFLDMOS. Moreover, based on this structure, the production of a gate below 0.5 μm is almost impossible. Furthermore, as the field oxidation is usually formed through thermal oxidation, air gaps cannot be formed in isolation regions to further reduce the capacitance, therefore the processing property is also limited.